1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method therefor.
2. Description of the Related Art
Not AND (NAND) flash memories being a nonvolatile semiconductor memory device are generally configured with a memory cell array and peripheral circuits. In the memory cell array, a memory cell transistor (hereinafter, simply “memory cell”) and a select gate transistor (hereinafter, simply “select gate”) are present, and in the peripheral circuits, a high voltage transistor and a low voltage transistor are present.
The memory cell has a function of retaining information, and the select gate, the high voltage transistor, and the low voltage transistor have a function as transistors, that is, a function of switching ON and OFF of a signal. Because a memory cell and the other transistors have different functions, the device configurations thereof are also different.
In a general NAND flash memory using floating gate devices, the memory cell has a five-layer structure in which a tunnel insulating film, a floating gate electrode, a gate insulating film, and a control gate electrode are sequentially layered on a substrate. On the other hand, other transistors have a three-layer structure in which a gate insulating layer and a gate electrode are layered on a substrate.
Generally, when a NAND flash memory using floating gate devices is manufactured, basically the same processes as those of other transistors are used up to the formation of a gate insulating film, except ion implantation. That is, a gate insulating film is also formed once in the transistors other than the memory cell. Thereafter, only the gate insulating film on the transistors other than the memory cell is opened, and a conductive film to be the control gate is layered thereon. This is also formed on the memory cell.
Through such a process, the memory cell has a structure in which the floating gate electrode and the control gate electrode are electrically insulated by the gate insulating film. The transistors other than the memory cell have a structure in which the floating gate electrode and the control gate electrode are electrically connected by the open gate insulating film, that is, a single-gate electrode structure.
On the other hand, in a NAND flash memory using metal oxide nitride oxide silicon (MONOS) devices, for example, as disclosed in Japanese Patent Application Laid-Open No. 2003-78043, the memory cell has a structure in which a tunnel insulating film, a charge-trap (charge storage) insulating film, a block insulating film, and a control gate electrode are sequentially layered on a substrate. However, such a manufacturing method as that of the NAND flash memory using floating gate devices cannot be employed for the flash memory using MONOS devices. This is because in the NAND flash memory using the MONOS devices, a structure corresponding to the floating gate is the charge-trap insulating film, and therefore, even if it is connected to the control gate electrode, the film does not work as a control gate. Therefore, for the flash memory using MONOS devices, the select gate is also manufactured by the same process as the memory cell, and has the same MONOS structure as the memory cell.
However, if the select gate is formed in the MONOS structure, the following problems are concerned. When low voltage is applied to the select gate at the time of reading from the memory cell, electrons are injected into the charge-trap (charge storage) insulating film of the select gate, and the threshold of the select gate changes. At this time, the threshold of the select gate changes to a higher value while readout voltage is fixed, and therefore current when the select gate is turned on becomes small, and the cell current is degraded. Such degradation of the cell current becomes a cause of erroneous readout.